Many direct memory access (DMA) controllers used for processing asynchronous data, such as bytes or other size blocks from terminals, transfer the data to memory via DMA operations as the blocks are received. This is done irrespective of the width of the memory bus, because it is not known if, and when, another block of data will be received. Moreover, for some environments, it may be necessary to effect DMA transfers relatively quickly. Such might be the case for echoing data back to terminals, for example. For slow rates of data arrival, e.g., 300 bits per second, the DMA transfer of bytes as they arrive carries little penalty. It is also appropriate when data arrives intermittently at slow rates. However, as data arrival rates increase, it becomes increasingly inefficient to perform a DMA operation for each block or byte of received data, if additional bus width is available for multiple data block transfers. Each DMA operation requires an arbitration for the memory bus which, in turn, consumes system resources.
The prior art contains many attempts to maximize bus usage and improve performance during DMA transfers. IBM Technical Disclosure Bulletin, Vol. 30, No. 12, May, 1988, page 211, describes a technique in which a DMA bus arbitration is requested only when the receive buffer contains a prescribed number of data blocks. This results in a larger data transfer to reduce the total amount of bus arbitrations. IBM Technical Disclosure Bulletin, Vol. 24, No. 10, Mar., 1982, page 5295, discloses an arrangement which provides for an automatic memory bus request for a subsequent DMA operation before a block presently being transferred is completed. This reduces buffer size requirements and the amount of microcode required for performing DMA transfers. U.S. Pat. No. 4,912,632, which issued on Mar. 27, 1990, relates to a memory subsystem controller including means for causing a DMA memory transfer to be interrupted at a cache memory line boundary to service a processor request and thereafter resume data transfer. U.S. Pat. application Ser. No. 297,778 relates to a DMA controller requiring no intervention from a main processor once the first of a series of block transfers has begun.
In many DMA architectures, the size and frequency of DMA transfers is fixed, as discussed above. In some applications, DMA performance can be improved by better understanding the data being processed. For example, in applications where data is being received rapidly, moving more data per DMA operation improves system performance because of the reduced overhead of negotiating for the bus. In applications where small or infrequent amounts of data are processed, moving the data as it is received may be optimal because of reduced latency of the processor acting on the information. The size of a typical DMA transfer is fixed at design time based on the constraints for that system. This poses a problem in that most applications can tolerate a relatively small variation in data rate before system performance deteriorates.